MN3101 Clock Driver IC Question

[pugdogs]

I'm trying to find out how many MN3007's I can drive with a single MN3101 clock driver IC. I was hoping to see if anyone may have used multiple BBD IC's with only a single clock driver on one of your projects. I want to see if it will drive 6 reliably. I have the parts now but I will not have time to test it until the weekend. I could use a multi-output clock buffer/driver but I don't have the room on the PCB.

The voltage rails are +/- 8VDC to the MN3007 and the MN3101.
fCP will need to be ~20KHz to keep the power dissipation at about 40mW max. R1=22K, R2=45K and C1=200pf
fOSC=40KHz

Any help would be great!

[Mark Hammer]

The number you can drive depends on the clock frequency you expect to run it at. The clock input pins on each BBD have input capacitance. When the total capacitance is summed (it's all in parallel), the result is that it corrupts clock pulses from the 3101 above some given frequency. Think of that input capacitance as being like a fixed lowpass filter on the clock pulse. As long as the clock stays well below the corner frequency of that filter, the clock is received exactly as sent. Round off those rising and falling edges with the input capacitance, and the switching action within the BBD*becomes less seamless and contiguous, resulting in a serious decline in audio quality.

The traditional workaround is that a buffer, which serves as current driver, is placed between the BBDs and whatever is being used as clock source. As the drive current of the clock signal increases, the BBD becomes more capable of accepting higher frequency clock pulses without the input capacitance causing a problem. I have it on good authority that you can clock an MN3007 (which Matsushita datasheets depict as crapping out around 100khz....without buffering) well past 1mhz.

[doctor]

The number you can drive depends on the clock frequency you expect to run it at. The clock input pins on each BBD have input capacitance. When the total capacitance is summed (it's all in parallel), the result is that it corrupts clock pulses from the 3101 above some given frequency. Think of that input capacitance as being like a fixed lowpass filter on the clock pulse. As long as the clock stays well below the corner frequency of that filter, the clock is received exactly as sent. Round off those rising and falling edges with the input capacitance, and the switching action within the BBD*becomes less seamless and contiguous, resulting in a serious decline in audio quality.

The traditional workaround is that a buffer, which serves as current driver, is placed between the BBDs and whatever is being used as clock source. As the drive current of the clock signal increases, the BBD becomes more capable of accepting higher frequency clock pulses without the input capacitance causing a problem. I have it on good authority that you can clock an MN3007 (which Matsushita datasheets depict as crapping out around 100khz....without buffering) well past 1mhz.

The simplest way to get the right answer is to refer to the MN3101 datasheets. In accordance with this document, the chip driving capability
is up to two MN3005 parts (equivalent to 8192 stages).
From this follows that one MN3101 can drive six MN3007 containing 6144 stages (less than 8192).

In other side, I as an electronics engineer, for my personal design
I would use one MN3101 for two MN3007 only.

Some words about clock frequency.
In accordance with MN3007 datasheets its clock frequency range
is 10-100KHz.
Using a frequency more than 100KHz for this chip is absolutely prohibited
(manufacturer does not warrant normal functioning of the chip, if even
one parameter isout of its defined margins).

It’s possible to use MN3101 at higher frequency (see more details in MN3101
datasheets) only with a suitable BBD allowing such high clock frequency.
Take into account that increasing the clock frequency increases frequency band, but decreases delay time.

In any case, good luck.

[Mark Hammer]

Just so we're clear, when I say "good authority", I do not mean a rumour circulating on-line. I mean I witnessed a demonstration of a functioning circuit using a 3007 and appropriate buffering.

The stated limitations and guaranteed ratings on the datasheets pertain to directly driving an BBD with an MN3101, in the absence of any buffering whatsoever. The 100khz boundary is set by what the 3101 can do when faced with the input capacitance of the BBD clock pins. While this two-chip arrangement is certainly the preferred application for purposes of simplifying the circuit, and keeping the cost and footprint to a minimum, there is no requirement to use the minimum arrangement. The industry is full of BBD-based circuits that use either CMOS buffers or other CMOS chips to provide a complementary clock with enough current drive to easily move beyond the recommended 100khz boundary for Matsushita chips. Implementations of the classic A/DA Flanger (which sweeps very high using a dual 512-stage BBD, so use of a 1024-stage device requires an even higher clock frequency) using an MN3007 are in abundance.

The reason why functioning is not guaranteed beyond 100khz in the datasheet is because the input capacitance of too many BBD stages causes progressive degradation of clock pulses that exceed that frequency. The clock pulse changes from perfectly square (which is what the chip needs to have a perfect changeover from sampled voltage A to sampled voltage B at the two complementary outputs) to something more in the direction of rounded trapezoidal. When that happens the switching action in the one channel inside the chip does not happen at exactly the same time as the switching action in the other channel. The result is that there can be gaps between successive samples at the output. When something is absent between successive samples, naturally you can expect the sound to be awful. The chip will still "work" (i.e., it won't explode or burn out), but it won't sound good at all. Hence, the recommendation to stay within certain maximum limits if you want a circuit that uses an MN3101 and MN3007 to sound good.

I guess the bigger question I have is why you want to drive multiple MN3007s when it would be simpler to drive an MN3008 or MN3005 or one of the MN3205 clones from Coolaudio. The Maxon AD-999 uses eight MN3007 chips, and enjoys a good reputation, but quite frankly it only did so because it was produced at a time after Panasonic had decided to discontinue the production of all BBDs (and Mike Matthews bought up the lion's share of the world's stock so that the EHX Memory Man could stay in production), but before Behringer decided to bankroll Coolaudio and start producing MN3207/3208/3205 clones for their own production needs. Once 4096-stage devices were back in production (finding their way into virtually every analog delay made since 2003 or so), there was simply no need to do what Maxon was doing with eight MN3007s with their own (ganged) clock chips, bias trimpots and balance trimpots.

[pugdogs]

Just so we're clear, when I say "good authority", I do not mean a rumour circulating on-line. I mean I witnessed a demonstration of a functioning circuit using a 3007 and appropriate buffering.

The stated limitations and guaranteed ratings on the datasheets pertain to directly driving an BBD with an MN3101, in the absence of any buffering whatsoever. The 100khz boundary is set by what the 3101 can do when faced with the input capacitance of the BBD clock pins. While this two-chip arrangement is certainly the preferred application for purposes of simplifying the circuit, and keeping the cost and footprint to a minimum, there is no requirement to use the minimum arrangement. The industry is full of BBD-based circuits that use either CMOS buffers or other CMOS chips to provide a complementary clock with enough current drive to easily move beyond the recommended 100khz boundary for Matsushita chips. Implementations of the classic A/DA Flanger (which sweeps very high using a dual 512-stage BBD, so use of a 1024-stage device requires an even higher clock frequency) using an MN3007 are in abundance.

The reason why functioning is not guaranteed beyond 100khz in the datasheet is because the input capacitance of too many BBD stages causes progressive degradation of clock pulses that exceed that frequency. The clock pulse changes from perfectly square (which is what the chip needs to have a perfect changeover from sampled voltage A to sampled voltage B at the two complementary outputs) to something more in the direction of rounded trapezoidal. When that happens the switching action in the one channel inside the chip does not happen at exactly the same time as the switching action in the other channel. The result is that there can be gaps between successive samples at the output. When something is absent between successive samples, naturally you can expect the sound to be awful. The chip will still "work" (i.e., it won't explode or burn out), but it won't sound good at all. Hence, the recommendation to stay within certain maximum limits if you want a circuit that uses an MN3101 and MN3007 to sound good.

I guess the bigger question I have is why you want to drive multiple MN3007s when it would be simpler to drive an MN3008 or MN3005 or one of the MN3205 clones from Coolaudio. The Maxon AD-999 uses eight MN3007 chips, and enjoys a good reputation, but quite frankly it only did so because it was produced at a time after Panasonic had decided to discontinue the production of all BBDs (and Mike Matthews bought up the lion's share of the world's stock so that the EHX Memory Man could stay in production), but before Behringer decided to bankroll Coolaudio and start producing MN3207/3208/3205 clones for their own production needs. Once 4096-stage devices were back in production (finding their way into virtually every analog delay made since 2003 or so), there was simply no need to do what Maxon was doing with eight MN3007s with their own (ganged) clock chips, bias trimpots and balance trimpots.

Thanks Mark and Doctor for your input!

From the original question regarding the driver capability, the operating frequency (fcp) is stated at 20KHz. I don't think I will even go with that value now. I need to maintain a lower power dissipation so I will recalculate my R/C values using 10KHz. Based on the specified capacitive drive of the MN3101 being approximately 4500pf and the maximum rated (Ccp) input clock capacitance of the MN3007 at 700pf, I should be able to operate 6.
However, I will need to take an existing design using a single BBD and load the input clocks with the maximum capacitive load and look at it (before and after) with a scope under similar operating voltages. My main concerns are amplitude, slew rate and zero crossing affects from the added capacitance to CP1 and CP2. (Why does the crossing point of CP1 and CP2 look so bad in the data sheet? Is that a result of low drive strength?)
I agree with your suggestion on having two BBD's per Clock driver but the PCB space was one of my issues from the start. I'm trying to pack 10 pound of stuff into a 1 pound bag. I have 80% of the PCB layout completed.

If I do decide to go with one driver for 2 BBD's, would it be better to use a single R1/C1 clock tap and share it with the other two clock drivers or have independent r/c values for each clock driver? The devices would be placed as close as possible to each other having the shortest possible matched impedance trace lengths.

Why not use a MN3008 or MN3005? Yes, it would be simpler to do it but I have a few reasons for doing this. Cost for 3005/8 and my current supply of 3007's. The V3205SD is only available with the V3102 and a $2000 minimum order from China. (from their website) I haven't spent much time looking eslewhere.

Panasonic MN3008 range from $8-$25
Panasonic MN3005 range from $20-$25
My current cost of the MN3007 = $1, MN3101 = $1.
Thanks.

[pugdogs]

OK. I see my error regarding the clock crossing comment. What is shown in the datasheet is the Input to the MN3007 and it's exceptable CP1/CP2 VX range. That makes me feel a lot better now. I'll post my scope captures later this week.

Thanks!

[Mark Hammer]

Geez, bud, you're looking in all the wrong places. Go here instead. If you have a surfeit of MN3007s, you can probably find plenty of people who would happily pay you good money for them, because they are i much shorter supply than 2048 and 4096-stage chips these days.

Results for ICs Delays, Echo and Special Function

[pugdogs]

Thanks for the link Mark. These prices look a lot better!