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Hey folks,
I apologize ahead of time for the long - windedness!
I have experienced this Ampeg model as well as some others that upon power down, buzz/pop/hum. I always assumed it was the unequal discharge of the +- 16V supplies that cause the Op amps to slam to one or the other rail upon power down and I still find that to be true.
I typically would just tell the cust that this is normal & they all do it, however this time the customer claimed it, what for it..."never did that before". So since I've always thought something could be done about this, I pursued it.
After hours of actually determining that this is a design issue & not an actual problem with the unit, I decided I had to add a ckt that would mute the output stage upon power down.
I'll try to attach a schemo that you can follow.
There is an existing mute ckt that is supposed to mute the output stage upon power up until ostensibly the power supplies have stabilized. It entails Q6 J111 FET and associated components that feed off of the -16VDC supply through a TCkt consisting of R- 1Meg resistor and C- 1uf cap to delay the gating off the FET. This ckt only works the first time you power it up or only if you wait for C-44 to discharge after the amp is turned off. IOW, if you power it right back up, the ckt won't mute the output. Also the timing of RC needs to be extended which I'll explain at the end.
As for the Mute @ Pwr Off ckt goes: Well, I'm not an engineer like most of us. I fart around with stuff like most of us based on some knowledge of how this shit works and a bunch of experimentation.
So, I decided to make what amounts to an AC detect ckt. At some point I'll scan the modified ckt and post it.
1) Connect a rect diode (I used a 1N4007 tho I think given the low current a 1N4841 would probably do) and connected the anode to one of the 40V secondary windings.
2) For moderate filtering I used a 0.047uf cap to ground on the Cathode to ground.
3) Then thru a 2.2M series dropping resistor and a divider resistor to ground of 470K on the other end of the resistor.
4) the 2.2M resistor feeds the gate of a J113 FET.
5) The S & D of the J113 then connect across R23 which is the FB loop of U3A pin 1 & 2.
So: Power up operation:
a. when the power is turned on, ac us immediately present at the 40V 2ndary of the transformer. It is slightly delayed by the filter cap 0.047uf but only milliseconds.
b. This is divided down by the 2 resistors & turns on FET J113 to allow Q6 FET to do the muting at power up.
Power down operation:
a. When power is removed, the gate of the added FET J113 is biased immediately ON which thereby mutes the output stage (or at least forces U3a to unity gain) which quiets the signal to the power stage,
AGAIN, I'm not an engineer & don't know if there are any consequences to having both Q6 FET & the added FET Source & Drains connected in parallel, I just know this seems to work really well to quiet the Thump, buzz, POP at power down for this model
Any suggestions from those smarter than I am, please chime in! Glen Whatley - Mars Amp Repair
I apologize ahead of time for the long - windedness!
I have experienced this Ampeg model as well as some others that upon power down, buzz/pop/hum. I always assumed it was the unequal discharge of the +- 16V supplies that cause the Op amps to slam to one or the other rail upon power down and I still find that to be true.
I typically would just tell the cust that this is normal & they all do it, however this time the customer claimed it, what for it..."never did that before". So since I've always thought something could be done about this, I pursued it.
After hours of actually determining that this is a design issue & not an actual problem with the unit, I decided I had to add a ckt that would mute the output stage upon power down.
I'll try to attach a schemo that you can follow.
There is an existing mute ckt that is supposed to mute the output stage upon power up until ostensibly the power supplies have stabilized. It entails Q6 J111 FET and associated components that feed off of the -16VDC supply through a TCkt consisting of R- 1Meg resistor and C- 1uf cap to delay the gating off the FET. This ckt only works the first time you power it up or only if you wait for C-44 to discharge after the amp is turned off. IOW, if you power it right back up, the ckt won't mute the output. Also the timing of RC needs to be extended which I'll explain at the end.
As for the Mute @ Pwr Off ckt goes: Well, I'm not an engineer like most of us. I fart around with stuff like most of us based on some knowledge of how this shit works and a bunch of experimentation.
So, I decided to make what amounts to an AC detect ckt. At some point I'll scan the modified ckt and post it.
1) Connect a rect diode (I used a 1N4007 tho I think given the low current a 1N4841 would probably do) and connected the anode to one of the 40V secondary windings.
2) For moderate filtering I used a 0.047uf cap to ground on the Cathode to ground.
3) Then thru a 2.2M series dropping resistor and a divider resistor to ground of 470K on the other end of the resistor.
4) the 2.2M resistor feeds the gate of a J113 FET.
5) The S & D of the J113 then connect across R23 which is the FB loop of U3A pin 1 & 2.
So: Power up operation:
a. when the power is turned on, ac us immediately present at the 40V 2ndary of the transformer. It is slightly delayed by the filter cap 0.047uf but only milliseconds.
b. This is divided down by the 2 resistors & turns on FET J113 to allow Q6 FET to do the muting at power up.
Power down operation:
a. When power is removed, the gate of the added FET J113 is biased immediately ON which thereby mutes the output stage (or at least forces U3a to unity gain) which quiets the signal to the power stage,
AGAIN, I'm not an engineer & don't know if there are any consequences to having both Q6 FET & the added FET Source & Drains connected in parallel, I just know this seems to work really well to quiet the Thump, buzz, POP at power down for this model
Any suggestions from those smarter than I am, please chime in! Glen Whatley - Mars Amp Repair
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