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Thread: question about capacitance and gate drive in power mosfets at high frequencies

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    Senior Member SoulFetish's Avatar
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    question about capacitance and gate drive in power mosfets at high frequencies

    I've been doing some reading on SMPS, and one of the areas of confusion I have is in regards to the effect of gate capacitance on switching frequency in power mosfets.
    Ciss seems to increase with power ratings in MOSFETS, which makes sense. This becomes more problematic as switching frequency increases, which also makes sense.
    The solution appears to be to allowing for higher output currents in the gate driving circuit, so the capacitance can charge and discharge very quickly (which is confusing to me). Unless, the input impedance drops significantly as frequency increases? That would make sense, but I always understood the gate to be a high impedance node. Any helpful explanations are appreciated.

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    Senior Member Old Tele man's Avatar
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    Analog analogy: think about "slew-rate" of signals through capacitors.

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    Probably way more than you ever wanted to know about driving MOSFETS. An application note explaining why you could/should use gate driver ICs and TI's Gate Drivers in particular.
    http://www.ti.com/lit/ml/slua618a/slua618a.pdf

    Cheers,
    Ian

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    Old Timer J M Fahey's Avatar
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    Quote Originally Posted by SoulFetish View Post
    I've been doing some reading on SMPS, and one of the areas of confusion I have is in regards to the effect of gate capacitance on switching frequency in power mosfets.
    Ciss seems to increase with power ratings in MOSFETS, which makes sense. This becomes more problematic as switching frequency increases, which also makes sense.
    The solution appears to be to allowing for higher output currents in the gate driving circuit, so the capacitance can charge and discharge very quickly (which is confusing to me).
    Not confusing, you sadly have a very real capacitor across gate to source, you *must* charge/discharge it when driving the Mosfet.
    Value is very high, think 2200pF or so ... not too much at Audio frequencies, a hard to drive one at 100/200kHz, and even more by a squarewave.
    Unless, the input impedance drops significantly as frequency increases?
    Yes.
    That would make sense, but I always understood the gate to be a high impedance node.
    Itīs "infinite impedance" (being glass insulated) at DC , but a current sucking one at typical SMPS frequencies.

    And lower: my "big" power amps , class AB, no switching involved, use IRFP250 and I had to add "driver transistors" just for that reason.

    And look at typical SMPS circuits, they always add bipolar buffers ... many times inside drive ICs themselves but they are there.

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    Juan Manuel Fahey

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    Senior Member trobbins's Avatar
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    Cgs is fairly constant with voltage change. Cgd is non-linear but very significant when it comes to smps switching, as drain voltage is rapidly changing.

    Yes, you need a driver that can push/pull as much current as quickly as possible.

    You then advance in to the realm of switching loss, where energy is used to charge and discharge fet capacitances, and so Fet manufacturers aim to optimise capacitances versus static resistances. Sometimes the circuit can use Cds and Cgd, but that can become tricky.

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    Senior Member SoulFetish's Avatar
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    Quote Originally Posted by Gingertube View Post
    Probably way more than you ever wanted to know about driving MOSFETS. An application note explaining why you could/should use gate driver ICs and TI's Gate Drivers in particular.
    http://www.ti.com/lit/ml/slua618a/slua618a.pdf

    Cheers,
    Ian
    Ian, thanks for the link to this app note. It's pretty great and is answering the questions I had, and answering the questions I didn't have. It's...uh, kind of a lot.
    So I'm reading through it real slow like.

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    Senior Member SoulFetish's Avatar
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    Quote Originally Posted by trobbins View Post
    Cgs is fairly constant with voltage change. Cgd is non-linear but very significant when it comes to smps switching, as drain voltage is rapidly changing.
    Right, this nonlinear capacitance is ultimately due to the miller effect, correct?
    So, does anyone cascode switching fets in this application to stabilize the input capacitance at the gate and minimize switching losses? or is that impractical or problematic?
    In the same respect, how would you keep the drain to source voltage at a fixed potential if the drain source voltage decreases as the turn on resistance lowers?
    (if I'm understanding it correctly)

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    Senior Member trobbins's Avatar
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    I prefer to see Cgd as a characteristic value that depends on the voltage across the capacitor. If you want Vds to transition between two states (on and off), then you have to appreciate the energy required to change the voltage across all the device capacitors Cgs, Cgd, Cds - for each change of state direction - and how that energy is related to the switching frequency, and using datasheet charge values to collate the variable nature of the capacitances. Switching loss is just one loss that has to be managed - it is often a low %, especially when using modern FETs and when limited by standard ferrite transformers or inductors. It becomes a very complex interplay of part choices/losses if you are trying to optimise some system aspect, like converter physical volume.

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    Word.

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