Jfet biasing - hiss

[lowell]

Crafted a lil preamp with a 2n5485. Max Id is 30ma. My supply is a single 24v. Please let me know if this is correct and also how to best reduce HISS. It's quite hissy.

.03 x 75% = .023 = 23ma (setting max current for 75%)

24 / .023 = 10ohms total resistance (Rd + Rs)

24 × .5 = 12v = Vd

So Rd and Rs will each be 5 ohms? Seems rather low

This is driving an amp input with standard 1M input 12ax7.

Thanks!

[Leo_Gnardo]

24 / .023 = 10ohms total resistance (Rd + Rs)

1000 ohms more like

take it from there...

[loudthud]

The 30mA rating is more of a "How much current can it stand as a switch" sort of thing. You don't use it for linear operation.

Idss for 2N5485 is 4 to 10mA, so it wise to bias them around 2mA or less. Randall used 2N5484 in the RG100 amps. Idss for that part is 1 to 5 mA.

[lowell]

1000 ohms more like

take it from there...

Whoops

[lowell]

Duh thanks guys. And the hiss? I have Rd 10k and Rs 4.7k. Quite hissy.

[R.G.]

Be careful about how you set up JFETs for breadboards. These things have useful gain well out in the VHF or UHF bands. It's easy to get the wrong kinds of parasitics working and have your JFET oscillating at frequencies where your 20MHz scope is completely blind. Be sure you keep leads and components short and direct, and properly bypass the power supply to ground as close to the JFET as you can get it.

I mention this because RF oscillation can be detected/heterodyned back down into audio, where it comes across as an "angry" hiss. It could also be an open wire on the gate bringing in untuned RF from the aether. Also like thermal hiss. They use small signal JFETs as RF front ends.

This probably isn't what's hitting you, but it ...could... be.

[Gingertube]

Even in a triode input stage the major contributor to noise is the grid stop resistor (gate stop for a JFET). To ensure freedom from parasitic oscillation, the value of the required gate/grid stop is inversely proportional to the device gm., about 5K minimum for a 12AX7 and maybe a 1/10th of that for the JFET which has much higher gm. ASIDE: The old tube boffins used to say 8/gm for the minimum grid stop resistor value. You could often (but not always) get away with less but that was the "rule of thumb" for good design.
From this you can see that the "standard" 68K everyone uses is too high and contributes un-necessary noise. Noise is proportional to resistance value.
If you have a gate stop resistor then reduce its value to say 470 Ohms. If you don't have one, then put it in. The resistor body needs to be hard up against the JFET gate pin or the triode socket grid pin. Surface Mount resistors are great for this and they solder nicely across a track cut when you have a PCB.
Cheers,
Ian

[lowell]

Thanks! So I have a 1meg stopper...per the Dumble ODS input. https://schematicheaven.net/dumbleamps/jfet.pdf

I read that Cgs is
Ciss - Crss. = 4pf

When calculating the gate stopper I find that if we want to cut Hz around 20Khz then a 2meg is the correct value.

A 470ohm stopper yields 85Khz!

Thoughts?

[eschertron]

Thanks! So I have a 1meg stopper...per the Dumble ODS input. https://schematicheaven.net/dumbleamps/jfet.pdf

I read that Cgs is
Ciss - Crss. = 4pf

When calculating the gate stopper I find that if we want to cut Hz around 20Khz then a 2meg is the correct value.

A 470ohm stopper yields 85Khz!

Thoughts?

OK, you mean 85Mhz, but I have no math to refute your assertion. My thought is only to tack a 1k-to-10k-ish resistor across the stopper just to hear the difference.

[lowell]

Right on. Wow I'm failing at math in this thread.

I'll try some parallel values and report back.

[nickb]

Thanks! So I have a 1meg stopper...per the Dumble ODS input. https://schematicheaven.net/dumbleamps/jfet.pdf

I read that Cgs is
Ciss - Crss. = 4pf

When calculating the gate stopper I find that if we want to cut Hz around 20Khz then a 2meg is the correct value.

A 470ohm stopper yields 85Khz!

Thoughts?

The design in that pdf would be very noisy*.

The capacitance between the gate and drain matters, often more that the gate to source capacitance due to the Miller effect. Think of it like this. Imagine you are driving a capacitor with 1V on one side and 0v on the other. You will measure the current 1/(wC). Now if you keep your 1V and apply 9V (opposite phase) to the other side than you current is 10/(wC) in other words you capacitor is looks 10x bigger than before. This is exactly what happens in the common source stage since an amplified version of the input appears on the drain. So the capacitor's value is (about) the gain of the stage bigger. And then the gate to source capacitance is added to that.

The gain is about gm* Zl (fully bypassed source) so the total effective input capacitance is Ciss + (1+gm*Zl)*Crss.

*I missed the 100pf across the 1Meg, so the input resistance noise would be below 1.5Khz. I'm also assuming the whatever drives it has a low impedance that shunts the noise from the 3.3Meg, otherwise it would be truly awful.