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uneumann (http://music-electronics-forum.com/t44917/) has designed a FET circuit for the first stage of a guitar amp; this stage sounds clean. Why? Is it because the JFET used as the lower device in the cascode is inherently more linear than a triode, or is it the result of the circuit design? The claim here is that it is the latter, and that it is the source resistor that linearizes the JFET. This is supported by modeling, showing that very similar results can be obtained with either device when the feedback from the source resistor is omitted. This post concludes with some suggestions for achieving this in practical FET circuit.
Norman Koren (Improved vacuum tube models for SPICE, Part 1) presents tube models intended for use in Spice. I will use them here in simple algebraic equations solved in Python-Scipy-broyden1 rather than using Spice. He presents two levels of modeling:
1. A simple one, curves in figure 1, uses the equation derived from simple physics in which the plate current is the sum of the plate voltage over the amplification factor and the grid voltage raIsed to the three halves power and divided by a constant. (equation 1).
2. a more complicated (new) equation that is derived from measurements (equation 4). The differences are very significant when plate voltage is high and the plate current low (figure 2, or look at measurements here: Biasing).
From these models, I have constructed a simple circuit using a 100K plate resistor and a power supply of 300V, using tube parameters for a 12AX7. The resulting equations are solved numerically for a sequence of grid voltages consisting of a bias voltage and a superposed sinusoidal variation. The level is set so that the output voltage is large, but not enough to make the grid go positive since there is no consideration of grid current here.
Results are shown here:
The blue line is the simple model; the green line is the more complicated (new) model. The differences are as expected: a triode does not turn off as easily as the simple model predicts. The red line is derived from a junction FET characteristic operation in the so called saturation region (where it behave as a current source). The red line has been derived from the drain current, scaled and shifted as necessary to get it to line up with the tube results. (This is what the upper device in the cascade does.)
In order to get this FET response, it is necessary to adjust both the bias point and gate signal voltage. The equation is IDS = IDSS*(1 - VGS/VP)**2. This equation is explained, for example, here: https://en.wikipedia.org/wiki/JFET. In order to get the red line to agree so well with the green line, it was necessary to adjust four things: the bias voltage, the input signal level, a dc shift, and a scale factor. Of course the agreement is not perfect. The tube response appears to have low levels of higher harmonics that the FET does not have since its model is a perfect square law. In practice, the FET might have such harmonics as well; I do not know.
In practice it is necessary to achieve the two degrees of freedom for adjustment of the FET while keeping the correct load on the pickup and avoiding excessive noise. One way is to start with a source follower. The pickup can be loaded as desired, the output impedance is low, and since JFETs with as low as 50 ohms of noise resistance are available, no significant noise is added. The signal level into the FET gain stage would be expected to need attenuation by several times. This can be accomplished by using a split source resistor in the source follower once the correct attenuation ration has been determined. The FET gain stage (also low noise) can be biased with a source resistor, but it must be bypassed, although it could be partially un-bypassed in some applications. The drain can go to the upper device of a cascode, or perhaps just a resistor in some applications.
tMod.py.zip
Norman Koren (Improved vacuum tube models for SPICE, Part 1) presents tube models intended for use in Spice. I will use them here in simple algebraic equations solved in Python-Scipy-broyden1 rather than using Spice. He presents two levels of modeling:
1. A simple one, curves in figure 1, uses the equation derived from simple physics in which the plate current is the sum of the plate voltage over the amplification factor and the grid voltage raIsed to the three halves power and divided by a constant. (equation 1).
2. a more complicated (new) equation that is derived from measurements (equation 4). The differences are very significant when plate voltage is high and the plate current low (figure 2, or look at measurements here: Biasing).
From these models, I have constructed a simple circuit using a 100K plate resistor and a power supply of 300V, using tube parameters for a 12AX7. The resulting equations are solved numerically for a sequence of grid voltages consisting of a bias voltage and a superposed sinusoidal variation. The level is set so that the output voltage is large, but not enough to make the grid go positive since there is no consideration of grid current here.
Results are shown here:
The blue line is the simple model; the green line is the more complicated (new) model. The differences are as expected: a triode does not turn off as easily as the simple model predicts. The red line is derived from a junction FET characteristic operation in the so called saturation region (where it behave as a current source). The red line has been derived from the drain current, scaled and shifted as necessary to get it to line up with the tube results. (This is what the upper device in the cascade does.)
In order to get this FET response, it is necessary to adjust both the bias point and gate signal voltage. The equation is IDS = IDSS*(1 - VGS/VP)**2. This equation is explained, for example, here: https://en.wikipedia.org/wiki/JFET. In order to get the red line to agree so well with the green line, it was necessary to adjust four things: the bias voltage, the input signal level, a dc shift, and a scale factor. Of course the agreement is not perfect. The tube response appears to have low levels of higher harmonics that the FET does not have since its model is a perfect square law. In practice, the FET might have such harmonics as well; I do not know.
In practice it is necessary to achieve the two degrees of freedom for adjustment of the FET while keeping the correct load on the pickup and avoiding excessive noise. One way is to start with a source follower. The pickup can be loaded as desired, the output impedance is low, and since JFETs with as low as 50 ohms of noise resistance are available, no significant noise is added. The signal level into the FET gain stage would be expected to need attenuation by several times. This can be accomplished by using a split source resistor in the source follower once the correct attenuation ration has been determined. The FET gain stage (also low noise) can be biased with a source resistor, but it must be bypassed, although it could be partially un-bypassed in some applications. The drain can go to the upper device of a cascode, or perhaps just a resistor in some applications.
tMod.py.zip
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