Question about LTP grid bias using JFET CCS tail.

[SoulFetish]

I was rereading some old threads on long tail pair phase inverters (This one in particuilar). Nickb posted some simulations comparing different current sources for the tail. The last example he shows has me confused though. In that one he uses a jfet current source. However, the grid bias is set to a 10V reference in the spice sim, but I don't see how(or where) he is deriving this voltage. Here is the original image:


I like this example. It appears to only require two components, including a single active device and I wanted to test it in an amp design where I can increase the headroom by dropping voltage across the tail to around 10V.
So, how would I go about designing a hybrid tube LTP using a jfet tail?

[loudthud]

In the simulation, the 10V just comes from V1, V4 or V5. In real life, you need either a Voltage divider from B+ or possibly a positive Voltage derived from the bias tap. Stability of the 10V might make a small difference in the amount of current, but that's not a huge issue. The current source in post 50 of the thread you linked has the advantage that it removes two capacitors from the signal path because the signals are now ground referenced. The disadvantage of that circuit is that the bias current for the PI (about 2mA) must come from the -16V rail. You can easily get that from a negative bias supply if it is derived from a bias tap off the PT.

[SoulFetish]

I like the idea using a negative supply. -16V with a 2mA load is easy to come by, even without a bias tap. maybe the easiest one would be to back bias the power supply if you can give up 16V from the B+
That way you can just short the non-inverting grid right to ground