Plate to grid capacitance???

[Chuck H]

I just noticed that on my SPICE models that if I plug a simulated pickup into a tube amp input that the frequency of the resonant peak drops. I know that the plate to grid capacitance of a tube (in this case a 12ax7) is multiplied by the gain of the circuit, making it a sufficient capcitance to cause this effect. I hadn't considered that this capacitance might be seen by the pickup. This makes sense to me now when I consider the circuit, but I'd like the experts (you know who you are ) to comment on this so I know if what I'm seeing is real or if it's an anomaly of the pickup or tube simulation in the models. If that makes sense.

Thanks

[pdf64]

The Miller capacitance should be less than 200pF. What capacitance have you got for the cable? I guess the lower that is, the greater the relative significance of the Miller effect.
But then a grid stopper should still act to ‘buffer’ the pickup from it. Did your sim include one?

[Chuck H]

Thanks for responding. I have a 600pF capacitance in circuit to represent the cable and the amp model has a 33k grid stop resistor. The amp input triode is the ubiquitous 100k plate, 1.5k/22uf cathode. I find that if I disconnect the pickup model from the input that adding another 115pf of capacitance simulates the effect. I too considered that the grid stop should offer some buffering, and maybe it does, but it's not significant. I think I know why, and I'm about to speculate beyond my actual understanding of electronics, but here's my theory...

The capcitance at the grid, as multiplied by stage gain, is an effect of the tubes plate resistance and feedback in the tube itself. Making the increased grid to plate capacitance a sort of "active" capacitance. Rendering the grid stop resistor less effective.

What I'm wondering about is if the results I'm seeing are real or the result of less than perfect tube or pickup modelling in SPICE.?.

[trobbins]

This wayback link (as I couldn't find a current link, although I do have a pdf of the webpage) may help appreciate the situation a bit. There is also grid-heater capacitance, and stray grid capacitance to ground - but these maybe all poultry compared to a cable to a pickup.

[Helmholtz]

Not much left to add.

I've measured the input capacitance of typical Fender amps at 100pF to 130pF (measurements are not very accurate, Zollner uses an average vaue of 150pF)
Nice to see that it drops to around 10pF with amp off (no gain - no Miller effect).

The 33k grid stopper will add some resonance damping, but can't really hide the capacitance because of the high source impedance of the PU.
Should be easy to see the effect of the grid stopper in simulation.

[Chuck H]

Thank you gents. I did understand that the small grid to plate capacitance of a tube would be multiplied by gain. I had thought that maybe this only presented at the plate output and did not know it could present itself as reactive with the pickup. Though it did make more sense to me when I considered the circuit I wanted to ask the higher minds because I'm not as scholarly in electronics. And...

This might be at least one reason guitar players have always preferred tube amps. Most solid state amps have a buffer for the input stage that doesn't multiply capacitance (and therefor a reduction in the resonant peak frequency). So players guitars sounded different plugged into solid state amps compared to the tube amps. Just thinking out loud.

[Helmholtz]

Any buffered pedal (like my TS-9) will isolate the guitar from the amp input and thus eliminate the effect.

[Chuck H]

I was looking through the attachment provided by trobbins. I noticed that the capacitor for the pickup model representing the pickups self capacitance is across only the inductor and the resistor. And not across the actual voltage source. Pretty much all other pickup models for SPICE and other CAD software has that capacitor across the entire circuit including the votage source. Considering the voltage source in the models are implemented as an ideal with zero impedance I didn't expect there to be any difference but I checked anyway. Here's what I got in my simulations. I'm wondering why there's a difference and what model arrangement is correct.?.

NOTE: The component values chosen are arbitrary and not intended to represent any particular pickup.

[Helmholtz]

I'm wondering why there's a difference and what model arrangement is correct.?.

The model in the article is wrong. Merlin made the same mistake in one of his books.
The wrong wiring of C4 creates an additional resonance.
There is no HF dip or notch in real measurements.
The PU's self-capacitance acts across the PU output and ground, so self-capacitance directly adds to the load capacitance with the vol pot fully up.

[Chuck H]

Great. Thank you.

[Chuck H]

The model in the article is wrong... The wrong wiring of C4 creates an additional series resonance..

Ok. Just to continue the discussion...

This will likely go beyond my full understanding and any answer may go over my head, but...

Why should there be a difference between the two two circuits if the voltage source is idealized with a zero impedance? Is there an elecronics reason or is this a SPICE/CAD error of some kind? Please forgive me if the answer is obvious to those that are more scholarly in electronics.

[pdf64]

That’s a darn good question!
I suppose the difference is that in the upper circuit, the bottom leg of C4 is held at 0V, whereas in the lower circuit, it’s bouncing around with the V2 signal.
Sometimes, especially with higher impedance circuits, the Norton equivalent works out being more helpful than the Thevanin.

[Chuck H]

Ok. I did an experiment. I used the lower circuit and bypassed the voltage source with a capacitor sufficient in value to bypass all frequencies (I used 1F). That resulted in the frequency curve seen in the upper circuit. So it would seem that SPICE and other CAD programs are modeled with Thevinan ideals.?. It still seems strange to me that the CAD voltage sources modeled as perfect demonstrate suficent impedance to cause the anomaly even though the same voltage model doesn't fail with a zero impedance paralleled to it. So...

I guess that if one wanted to use a CAD voltage source as a current source just make sure to parallel something like a 1F capacitor with it.?. This is beyond my full understanding but may prove useful at some point if I need a true "current source" rather than a "voltage source" for a simulation.

EDIT: I know Spice has a current source model in the inventory but that didn't work in the simulation.

[Helmholtz]

Lemme try.

The wrong circuit treats the PU as a passive 2 terminal filter that is connected to an outer source.
Without a load there would be no current.

In reality the PU generates its own voltage, which means the source (EMF) must be contained within the loop between inductance and capacitance.
Even without a load there's a current flowing in the loop.
PU capacitance appears between the coil wire ends, i.e. across the output terminals.

Looking at the wrong circuit one can see that the current between external source and a resistive PU load passes a series wired parallel resonant circuit (PRC).
A PRC has an impedance maximum at resonance, so this circuit develops a notch instead of a resonant peak.

With the correct circuit L and C are wired in series with the signal current. This wiring produces a signal maximum at the hot end of the capacitance, i.e. a resonant peak.

[Helmholtz]

EDIT: I know Spice has a current source model in the inventory but that didn't work in the simulation.

You can't just replace a voltage source with a current source.
A voltage source is wired in series while a current source needs to be wired in parallel.
Try connecting the current source to the ends of the inductance.