I'm working on a Univox Micro Fazer and have determined that the weak phasing is a result of weak JFETs. Everything else looks and works without a problem and I pulled the original 2SK34's and they measured between -0.74v to -0.89v on R.G.'s improved JFET Matcher (IJM). Which I think is not good?
So, I bought 50 BF244A JFETs, measured them on the IJM, setup my bench to record values and categorized 3 sets of 4. One particular set has a value of -1.06v. I put these in and the phasing is still weak.
So here are my questions
1. What is considered an optimal Vgs-off value (using the IJM) for the standard Phase 90 circuit?
2. Vgs-off means the voltage at which the JFET turns off. If the JFET is biased at 4.5vdc, is the LFO voltage (at the Gate) the control that turns the JFET on and off... I would think the answer is yes! Vgs-off must be the voltage difference between the Gate and the source...correct?
3. If question 2 is correct, then the optimal Vgs-off is dependent upon the sweep range of the LFO... correct?
4. If this is true then the LFO voltage determines the optimal voltage difference between the gate and the source and I should be able to reduce the sweep range to match my Vgs-off values of the JFETS ...correct?
I better stop there before I either answer my own questions or drive myself into a JFET induced coma.
Thanks in advance,
CJ
So, I bought 50 BF244A JFETs, measured them on the IJM, setup my bench to record values and categorized 3 sets of 4. One particular set has a value of -1.06v. I put these in and the phasing is still weak.
So here are my questions
1. What is considered an optimal Vgs-off value (using the IJM) for the standard Phase 90 circuit?
2. Vgs-off means the voltage at which the JFET turns off. If the JFET is biased at 4.5vdc, is the LFO voltage (at the Gate) the control that turns the JFET on and off... I would think the answer is yes! Vgs-off must be the voltage difference between the Gate and the source...correct?
3. If question 2 is correct, then the optimal Vgs-off is dependent upon the sweep range of the LFO... correct?
4. If this is true then the LFO voltage determines the optimal voltage difference between the gate and the source and I should be able to reduce the sweep range to match my Vgs-off values of the JFETS ...correct?
I better stop there before I either answer my own questions or drive myself into a JFET induced coma.
Thanks in advance,
CJ
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